Orange Crab¶

Reference¶

Getting Started

Get Toolchain¶

# see: https://github.com/open-tool-forge/fpga-toolchain/releases

read os <<< "linux"
read arch < <( uname -i )

read url < <(
  curl "https://api.github.com/repos/open-tool-forge/fpga-toolchain/releases/latest" \
    | jq -r \
      --arg os "${os}" \
      --arg arch "${arch}" \
      '
        .assets[]
          | select(.name | contains($os + "_" + $arch))
          | select(.name | endswith(".tar.gz"))
          | .browser_download_url
      '
)

curl -LO "${url}"
tar -xvf "${url##*/}"

export PATH="$(readlink -f ./fpga-toolchain/bin/):${PATH}"

yosys -V
nextpnr-ecp5 -V

udev Rule¶

/etc/udev/rules.d/99-orangecrab.rules

ATTRS{idVendor}=="1209", ATTRS{idProduct}=="5af0", MODE="0666", GROUP="plugdev", TAG+="uaccess"

udevadm control --reload-rules

Examples¶

git clone https://github.com/gregdavill/OrangeCrab-examples
cd OrangeCrab-examples/verilog/blink
make

Press button, and plug in... LED should fade RGB.

make dfu

LED should fade in/out Orange, and then switch to the new bitstream.

nMigen¶

NOTE: the yosys toolchain must still be on your ${PATH}.

cd OrangeCrab-examples/nmigen

python3 -m venv venv
. venv/bin/activate

pip install --upgrade git+https://github.com/nmigen/nmigen-boards#egg=nmigen-boards

# enter bootloader

python blink.py

LiteX¶

Get an Older Toolchain¶

Current releases have a problem with LiteX SoCs... possibly a Yosys bug. Instead, we need to use a version from before 1^st July 2020.

read os <<< "linux"
read arch < <( uname -i )
read date < <( TZ='UTC' date -d '1 Jul 2020' +'%s' )

read url < <(
  curl "https://api.github.com/repos/open-tool-forge/fpga-toolchain/releases?per_page=100" \
    | jq -r \
      --arg os "linux" \
      --arg arch "$(uname -i)" \
      --arg date "${date}" \
      '
        [ .[] | select((.published_at | fromdateiso8601) < ( $date | tonumber )) ]
          | first
          | .assets[]
          | select(.name | contains($os + "_" + $arch))
          | select(.name | endswith(".tar.gz"))
          | .browser_download_url
      '
)

curl -LO "${url}"
tar -xvf "${url##*/}"

export PATH="$(readlink -f ./fpga-toolchain/bin/):${PATH}"

yosys -V
nextpnr-ecp5 -V

Get RISC-V Toolchain¶

# see: https://www.sifive.com/software

curl -LO "https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz"
tar -xvf riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz

export PATH="$(readlink -f ./riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin):${PATH}"

riscv64-unknown-elf-gcc -v

Build LiteX SoC¶

cd OrangeCrab-examples/litex

python3 -m venv venv
. venv/bin/activate

pip install --upgrade git+https://github.com/litex-hub/pythondata-software-compiler_rt.git

python SoC-CircuitPython.py

Build CircuitPython¶

git clone https://github.com/gregdavill/circuitpython.git -b orangecrab --recurse-submodules
make BOARD=orangecrab -C circuitpython/ports/litex

Combine SoC and CircuitPython Firmware, and Flash¶

ln -s circuitpython/ports/litex/build-orangecrab/firmware.bin
python combine.py
dfu-util -D combine.dfu